QEMU 10.2 revises security policies, modernizes the crypto subsystem, and accelerates asynchronous I/O under Linux.

India has formally introduced DHRUV64, a 64-bit, dual-core microprocessor based on the RISC-V instruction set, developed by the Centre for Development of Advanced Computing (C-DAC) under the national ...

Qualcomm has announced the acquisition of Ventana Micro Systems, a move aimed at strengthening its CPU portfolio through advanced RISC-V technology. Qualcomm boosts CPU development with acquisition ...

Qualcomm has acquired Ventana Micro Systems Inc., a move aimed at bolstering its capabilities in the RISC-V instruction set architecture (ISA) and custom CPU development. The acquisition integrates ...

The acquisition reinforces Qualcomm's commitment and leadership in the development of the RISC-V standard and ecosystem. Ventana’s expertise in RISC-V instruction set development enhances Qualcomm’s ...

RISC-V is an open-source Instruction Set Architecture (ISA) that rapidly transforms the CPU design and development landscape. Unlike proprietary ISAs, RISC-V allows free access to architecture ...

HAIFA, Israel & SANTA CLARA, Calif.--(BUSINESS WIRE)--proteanTecs®, a global leader in deep data solutions for electronics health and performance monitoring, and Akeana, a provider of high-performance ...

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

Once a hyperscaler or a cloud builder gets big enough, it can afford to design custom compute engines that more precisely match its needs. It is not clear that the companies that make custom CPUs and ...

Forbes contributors publish independent expert analyses and insights. Marco Chiappetta is a technologist who covers semiconductors and AI. SiFive just announced an array of new additions to its ...